This invention relates to-an electronic module having a stack of IC chip layers secured together, and having a plane on the stack which provides terminals for electrical connection to circuitry on a substrate to which the stack is mounted.
The assignee of this application (Irvine Sensors Corporation) has developed "3-D" IC chip stacks over a period of many years. The technology is sometimes referred to as Z-technology because Z-axis electronics are connected to a matrix of electrical leads located on an X-Y access plane. Initially, the stacks were intended to be used as analog signal-processing ICs for infrared focal plane sensors. More recently, the stacks have been designed for use in computer systems, with emphasis on the use of such stacks to obtain memory densification.
Two types of stack configurations have been developed: the full stack, which may be referred to as a "sliced bread" stack, because its layers are perpendicular to the supporting substrate; and the short stack, which may be referred to as a "pancake" stack, because its layers are parallel to the supporting substrate. The supporting substrates have generally been formed of dielectric material, in order to minimize short-circuiting risks.
The present application is concerned primarily with the substrate, to which the chip stack is connected by both electrical and mechanical connections. Both the electrical and mechanical connections may be provided by solder bumps, i.e., by "flip chip" bonding. However, the electrical connections can be made by other means, such as an elastomeric interconnect. Or, where a "pancake" stack is used, the electrical connections may be wire bonds.
An example of an early 3-D IC chip stack designed for "focal plane" use in infrared sensing systems is shown in common assignee U.S. Pat. No. 4,551,629 (filing date Sep. 16, 1980). The focal plane of the stack has a two-dimensional array of photo detectors. The back plane of the stack has wiring which leads to the outer edges of a flat insulating board secured against the back plane.
The first 3D IC chip stack for computer use is common-assignee U.S. Pat. No. 4,646,128 (filing date Jul. 25, 1983), in which the chip stack is secured to "flat insulator members", the edges of which have electrical leads connecting to exterior circuitry.
The next development in 3D IC chip stacks for computer use is shown in common assignee U.S. Pat. No. 4,706,166 (filing date Apr. 25, 1986). In that patent, the chip stack is a "sliced bread" type, in which the chips are perpendicular to a flat supporting substrate. The stack and substrate in the patent are secured together by aligned solder bumps, and the substrate is "formed of silicon, because it has the same thermal coefficient of expansion as the stack, and it is transparent to infrared radiation". Of course, an intervening insulation material is required between the silicon chip stack and the silicon substrate.
Although the patent mentioned in the preceding paragraph used a silicon substrate combined with a stack of silicon chips, the inventions disclosed in the present application, which may combine a silicon substrate with a stack of silicon chips, were not suggested by Irvine Sensors inventors until several years later (1990 or 1991). In the interim, the Irvine Sensors preference was to use a ceramic substrate with the chip stack.
Beginning in 1991, Irvine Sensors submitted several proposals to the U.S. Government, in which it suggested that use of an IC chip as the "substrate" or "backplane" attached to the access face of a stack of chips could provide significant benefits. This substrate layer, referred to as an "active substrate" would contain its own IC circuits, which would provide the interface circuitry between the memory IC circuits in the stack and the overall external computer system bus.
Over a period of time, the subject was analyzed, and certain functions were found to be particularly appropriate for inclusion in an active substrate. Three proposals were made by Irvine Sensors in 1991 and 1992, containing, respectively the following suggestions:
"Laptop and notepad computers are two examples of the many applications that require low power, low weight mass storage. 3D packaging solves the weight and volume issues but available packageable memory devices are unsatisfactory. Non-volatile devices such as FRAMs and Flash suffer from cost and limited life. DRAMs consume too much power as do most SRAMs manufactured on high volume, low cost DRAM lines. Specialty low power SRAMs exist but are either too expensive or unavailable for 3D packaging. The proposed innovation combines high density 3D packaging of conventional, domestically available SRAM devices with active mounting substrates that control the device power dissipation in the standby mode. Furthermore, the innovation lends to substantially lower voltage operation resulting in very large power savings in both operating and standby modes. A 50 megabyte hard disk replacement will consume 0.5 cubic inches and have negligible impact on battery rundown time. In addition, access times will reduce from milliseconds to less than 100 nanoseconds." PA1 "The proposed innovation is a fault-tolerant 3D memory module comprising: a 3D stack of high performance memory ICs custom designed for stacking; an active substrate ASIC which acts as a motherboard for the stack providing I/O, control, fault-tolerance and "smart memory" functions. A packaged production module providing 64 MB of memory will occupy a footprint of approximately 2 cm.times.2 cm, dissipate less than 7W and have an effective bandwidth greater than 500 MB per second. Ten year reliability of a two module system is greater than 0.9999. Additionally, use of the "smart memory" functions improves computational throughput by two to three orders of magnitude (depending on application). Development of the underlying technology (3D Stack-On-Active-Substrate) will lead to new high performance computer architectures and new computing paradigms based on: smart memories; massive parallelism in small, high speed, low power packages; and dynamically reconfigurable architectures." PA1 "The proposed innovation is a 3D hybrid wafer scale radiation/fault tolerant cache memory module incorporating an active substrate for the implementation of functions such as module I/O, EDAC, SEU scrubbing and memory mapping/ reconfiguration. Next generation space based computing systems such as the Space Station Freedom (SSF) computer will require large high speed cache memories to achieve required throughputs. Commercially available processors such as the Intel 80486 do not implement fault tolerance functions in their internal caches, thus making them unsuitable for space applications. External caches/controllers have been designed for some machines, but do not adequately address the fault tolerance or power/weight/volume requirements peculiar to the space environment. The objective of this proposal is the design of a cache memory module suitable for use in the 80X86 based space borne computer.